1. Field of the Invention
This specification relates to a gate driving circuit, and particularly, to a gate driving circuit capable of improving yield by ensuring a design margin and reducing a fabricating cost, and a liquid crystal display device having the same.
2. Background of the Invention
In general, a liquid crystal display (LCD) device displays an image by adjusting light transmittance of liquid crystal (LC) having dielectric anisotrophy using an electric field.
The LCD device includes a liquid crystal (LC) panel for displaying image data input from the exterior, and a driving circuit for driving the LC panel.
Recently, an LCD device, which employs a Gate In Panel (GIP) type, in which the driving circuit is mounted in the LC panel to reduce a fabricating cost and minimize power consumption.
FIG. 1 shows a GIP type LCD device according to the related art.
As shown in FIG. 1, a plurality of gate lines GL and data lines DL are arranged on an LC panel 10 with perpendicularly intersecting with each other, and a pixel is disposed at each intersection between the gate line GL and the data line DL. Each pixel includes a thin film transistor (TFT) and a pixel electrode connected to the TFT. Here, the TFT operates in response to a signal input from the gate line GL and allows an electrical connection between the data line DL and the pixel electrode.
A gate driving circuit 20 receives a control signal CONT1 from a timing controller 40 to generate a gate signal, and sequentially supplies the generated gate signal to the gate line GL to turn on the corresponding TFT connected to the gate line GL.
A data driving circuit 30 receives a control signal CONT2 and an image signal DAT from the timing controller 40 to apply a data voltage corresponding to the image signal DAT to the data line DL. Such data voltage supplied for each pixel forms an electric field between the pixel electrode and a common electrode to adjust transmittance of an LC layer, accordingly, an image is displayed.
The timing controller 40 controls the gate driving circuit 20 and the data driving circuit 30, and applies the control signal CONT1 to the gate driving circuit 20 and the control signal CONT2 and the image signal DAT to the data driving circuit 30.
Here, the gate driving circuit 20 may be formed on the LC panel 10 at the same time of a TFT process, and the data driving circuit 30 may be formed on the LC panel 10 or may not be formed thereon.
FIG. 2 shows the gate driving circuit of FIG. 1, and FIG. 3 is a timing diagram showing a start signal and a clock signal used in the gate driving circuit.
As shown in FIG. 2, the gate driving circuit 20 includes a shift register 21 having N stages, which are driven by a start signal Vst and four clock signals CLK1 to CLK4 applied (output) from the timing controller 40, and a dummy shift register 23 having first and second dummy stages.
Among the N stages, the first stage receives the start signal Vst and the first clock signal CLK1 to output a gate signal Voutl on the first gate line. Accordingly, the Nth stage receives a gate signal Vout(N−2) of N−2th shift register as a start signal and the fourth clock signal CLK4 to output an Nth gate signal VoutN.
Here, each of the N stages first outputs a gate signal, namely, a high level gate signal, and then outputs a low level gate signal by a reset signal RESET. For example, the first stage first outputs the high level gate signal Vout1, and then outputs a low level gate signal by receiving a gate signal Vout3 of the third stage as the reset signal RESET.
In the meantime, each of the N−1th stage and the Nth stage should first output a high level gate signal and then output a low level gate signal by receiving a reset signal. However, the timing controller 40 of FIG. 1 does not separately provide a reset signal for resetting the N−1th stage and the Nth stage. Hence, the dummy shift register 23 is further formed on the LC panel 10 so as to provide a reset signal to each of the N−1th stage and the Nth stage.
FIG. 4 shows a bidirectional gate driving circuit for the GIP type LCD device.
As shown in FIG. 4, the bidirectional gate driving circuit 50 includes a shift register 51 having N stages, which are driven by a start signal Vst and four clock signals CLK1 to CLK4 output from the timing controller 40, and first and second dummy gate driving units 53 and 55 having first and second dummy stages, respectively.
The shift register 51 having the N stages are the same as the shift register 21 of FIG. 2 in configuration and operation. The first and second dummy gate driving units 53 and 55 include first and second dummy stages, respectively, although not shown.
Upon operating as a forward gate driving circuit, the first dummy gate driving unit 53 is driven by a start signal Vst and first and second clock signals CLK1 and CLK2 received from the timing controller 40, and the shift register 51 having the N stages is driven by the start signal Vst, the first and second clock signals CLK1 and CLK2 and a reset signal RESET output from the first dummy gate driving unit 53.
As such, for the forward operation of the gate driving circuit 50, each of the N−1th stage and the Nth stage of the shift register 51 should first output a high level gate signal and then output a low level gate signal by receiving the reset signal RESET, as shown in FIG. 2. However, the timing controller 40 of FIG. 1 does not separately provide reset signals for resetting the N−1th stage and the Nth stage, the first dummy gate driving unit 53 is further formed on the LC panel 10 to provide the reset signals to the N−1th stage and the Nth stage.
Also, upon operating as a backward gate driving circuit, the second dummy gate driving unit 55 is driven by the start signal Vst and the first and second clock signals CLK1 and CLK2 output from the timing controller 40, and the shift register 51 having the N stages is driven by the start signal Vst, the first and second clock signals CLK1 and CLK2 and the reset signal RESET output from the second dummy gate driving unit 55. Here, since the gate driving circuit operates in 25 the backward manner, the first stage operates as the Nth stage, the second stage as the N−1th stage, and the Nth stage as the first stage.
Each of the N−1th stage and the Nth stage of the shift register 51 should first output a high level gate signal and then output a low level gate signal by receiving a reset signal RESET. However, the timing controller 40 of FIG. 1 does not separately provide a reset signal for resetting the N−1th stage and the Nth stage. Hence, the second dummy gate driving unit 55 is further formed on the LC panel 10 so as to provide a reset signal to each of the N−1th stage and the Nth stage.
As such, upon employing the GIP type gate driving circuit of FIG. 2 and the GIP type bidirectional gate driving circuit of FIG. 4, the dummy shift register 23 and the first and second dummy gate driving units 53 and 55 should be respectively formed on the LC panel 10, which causes reduction of a design area and difficulty in ensuring a process margin, resulting in an increase in a fabricating cost of the LC panel 10.
Referring to part ‘A’ of FIG. 3, the first and second clock signals CLK1 and CLK2 additionally have signal waveforms for operating the dummy shift register 23 and the first and second dummy gate driving units 53 and 55, thereby causing an increase in a memory capacity within the timing controller 40.
Furthermore, in the structure of the GIP type bidirectional gate driving circuit shown in FIG. 4, since the start signal Vst output from the timing controller 40 is input to the shift register 51 not directly but via the first and second dummy gate driving units 53 and 55, an output characteristic of a signal may be lowered. Consequently, when the performance of the first and second dummy gate driving units 53 and 55 is degraded due to a long-term driving of the bidirectional gate driving circuit, the output of the gate signals output from the shift resistor 51 is lowered.